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NB6N14S 3.3 V 1:4 AnyLevelt Differential Input to LVDS Fanout Buffer/Translator
The NB6N14S is a differential 1:4 Clock or Data Receiver and will accept AnyLevelt differential input signals: LVPECL, CML or LVDS. These signals will be translated to LVDS and four identical copies of Clock or Data will be distributed, operating up to 2.0 GHz or 2.5 Gb/s, respectively. As such, the NB6N14S is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock or Data distribution applications. The NB6N14S has a wide input common mode range from GND + 50 mV to VCC - 50 mV. Combined with the 50 W internal termination resistors at the inputs, the NB6N14S is ideal for translating a variety of differential or single-ended Clock or Data signals to 350 mV typical LVDS output levels. The NB6N14S is offered in a small 3 mm x 3 mm 16-QFN package. Application notes, models, and support documentation are available at www.onsemi.com. The NB6N14S is a member of the ECLinPS MAXt family of high performance products.
Features http://onsemi.com MARKING DIAGRAM*
16 1
1 QFN-16 MN SUFFIX CASE 485G A L Y W G
NB6N 14S ALYW G G
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
* * * * * * * * * *
Maximum Input Clock Frequency > 2.0 GHz Maximum Input Data Rate > 2.5 Gb/s 1 ps Maximum RMS Clock Jitter Typically 10 ps Data Dependent Jitter 380 ps Typical Propagation Delay 120 ps Typical Rise and Fall Times VREF_AC Reference Output TIA/EIA - 644 Compliant Functionally Compatible with Existing 3.3 V LVEL, LVEP, EP, and SG Devices These are Pb-Free Devices
(Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D.
Q0 Q0
Q1 IN W VT 50 W /IN 50 Q1
Q2 Q2
VOLTAGE (130 mV/div)
EN (LVTTL/CMOS) VREF_AC Device DDJ = 10 ps
D
Q Q3 Q3
Figure 1. Logic Diagram ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet.
Figure 2. Typical Output Waveform at 2.488 Gb/s with PRBS 223-1 (VINPP = 400 mV; Input Signal DDJ = 14 ps)
TIME (58 ps/div)
(c) Semiconductor Components Industries, LLC, 2007
January, 2007 - Rev. 3
1
Publication Order Number: NB6N14S/D
NB6N14S
Q0 16 Q1 Q1 Q2 Q2 1 2 NB6N14S 3 4 5 Q3 6 Q3 7 VCC 8 EN Q0 15 VCC GND 14 13 12 IN 11 VT 10 VREF_AC 9 IN Exposed Pad (EP)
Table 1. TRUTH TABLE
IN 0 1 x IN 1 0 x EN 1 1 0 Q 0 1 0 (Note 1) Q 1 0 1 (Note 1)
1. On next transition of the input signal (IN).
Figure 3. NB6N14S Pinout, 16-pin QFN (Top View)
Table 2. PIN DESCRIPTION
Pin 1 2 3 4 5 6 7 8 Name Q1 Q1 Q2 Q2 Q3 Q3 VCC EN I/O LVDS Output LVDS Output LVDS Output LVDS Output LVDS Output LVDS Output - LVTTL / LVCMOS Input Description Non-inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. Inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. Non-inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. Inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. Non-inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. Inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. Positive Supply Voltage. Synchronous Output Enable. When LOW, Q outputs will go LOW and Qb outputs will go HIGH on the next negative transition of IN input. The internal DFF register is clocked on the falling edge of IN input; see Figure 19. The EN pin has an internal pullup resistor and defaults HIGH when left open. Inverted Differential Input The VREF_AC reference output can be used to rebias capacitor-coupled differential or single-ended input signals. For the capacitor-coupled IN and/or INb inputs, VREF_AC should be connected to the VT pin and bypassed to ground with a 0.01 mF capacitor. Internal 100 W Center-tapped Termination Pin for IN and IN Non-inverted Differential Input. (Note 2) Negative Supply Voltage. Positive Supply Voltage. Non-inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. Inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. The Exposed Pad (EP) on the QFN-16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat-sinking conduit. The pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to GND on the PC board.
9 10
IN VREF_AC
LVPECL, CML, LVDS LVPECL Output
11 12 13 14 15 16 -
VT IN GND VCC Q0 Q0 EP
LVPECL Output LVPECL, CML, LVDS - - LVDS Output LVDS Output -
2. In the differential configuration, when the input termination pin (VT) is connected to a termination voltage or left open, and if no signal is applied on IN/IN inputs, then the device will be susceptible to self-oscillation.
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NB6N14S
Table 3. ATTRIBUTES
Characteristics Moisture Sensitivity (Note 3) Flammability Rating ESD Protection Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34 Human Body Model Machine Model Value Level 1 UL 94 V-0 @ 0.125 in > 2 kV > 200 V 225
Table 4. MAXIMUM RATINGS
Symbol VCC VIN IIN IOSC Parameter Positive Power Supply Positive Input Input Current Through RT (50 W Resistor) Output Short Circuit Current Line-to-Line (Q to Q) Line-to-End (Q or Q to GND) TIA/EIA - 644 Compliant VREF_AC Sink/Source Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (Note 4) Thermal Resistance (Junction-to-Case) Wave Solder Pb-Free 0 lfpm 500 lfpm 1S2P (Note 4) QFN-16 QFN-16 QFN-16 QFN-16 Condition 1 GND = 0 V GND = 0 V Static Surge Q or Q to GND Q to Q Continuous Continuous VIN VCC Condition 2 Rating 3.8 3.8 35 70 12 24 "0.5 -40 to +85 -65 to +150 41.6 35.2 4.0 265 Unit V V mA mA mA
IREF_AC TA Tstg qJA qJC Tsol
mA C C C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. JEDEC standard multilayer board - 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB6N14S
Table 5. DC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V, TA = -40C to +85C
Symbol ICC Vth VIH VIL VREF_AC VIHD VILD VCMR VID RTIN VOD DVOD VOS DVOS VOH VOL VIH VIL IIH IIL Characteristic Power Supply Current (Note 9) Min Typ 65 Max 100 Unit mA
DIFFERENTIAL INPUTS DRIVEN SINGLE-ENDED (Figures 10, 11, 15, and 17) Input Threshold Reference Voltage Range (Note 8) Single-ended Input HIGH Voltage Single-ended Input LOW Voltage Reference Output Voltage (Note 11) GND +100 Vth + 100 GND VCC - 1.600 100 GND GND + 50 100 40 50 VCC - 1.425 VCC - 100 VCC Vth - 100 VCC - 1.300 VCC VCC - 100 VCC - 50 VCC 60 mV mV mV V
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 6, 7, 8, 9, 16, and 18) Differential Input HIGH Voltage Differential Input LOW Voltage Input Common Mode Range (Differential Configuration) Differential Input Voltage (VIHD - VILD) Internal Input Termination Resistor mV mV mV mV W
LVDS OUTPUTS (Note 5) Differential Output Voltage Change in Magnitude of VOD for Complementary Output States (Note 10) Offset Voltage (Figure 14) Change in Magnitude of VOS for Complementary Output States (Note 10) Output HIGH Voltage (Note 6) Output LOW Voltage (Note 7) 900 250 0 1125 0 1 1425 1075 1 450 25 1375 25 1600 mV mV mV mV mV mV
LVTTL/LVCMOS INPUTS Input HIGH Voltage (Note 7, 8) Input LOW Voltage (Note 7, 8) Input HIGH Current Input LOW Current 2.0 GND -150 -150 VCC 0.8 150 150 V V mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. LVDS outputs require 100 W receiver termination resistor between differential pair. See Figure 13. 6. VOHmax = VOSmax + 1/2 VODmax. 7. VOLmax = VOSmin - 1/2 VODmax. 8. Vth is applied to the complementary input when operating in single-ended mode. 9. Input termination pins open, D/D at the DC level within VCMR and output pins loaded with RL = 100 W across differential. 10. Parameter guaranteed by design verification not tested in production. 11. VREF_AC used to rebias capacitor-coupled inputs only (see Figures 10 and 11).
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NB6N14S
Table 6. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V; (Note 12)
-40C Symbol finMax VOUTPP Characteristic Maximum Input Clock Frequency Output Voltage Amplitude (@ VINPPmin) fin 1.0 GHz (Figure 4) fin= 1.5 GHz fin= 2.0 GHz Maximum Operating Data Rate Differential Input to Differential Output Propagation Delay Setup Time Hold Time Within Device Skew (Note 17) Device-to-Device Skew (Note 16) RMS Random Clock Jitter (Note 14) Deterministic Jitter (Note 15) fin = 1.0 GHz fin = 1.5 GHz fDATA = 622 Mb/s fDATA = 1.5 Gb/s fDATA = 2.488 Gb/s 100 Q, Q 60 120 Min 2.0 220 200 170 1.5 300 300 500 350 300 270 2.5 450 60 70 5 30 0.5 0.5 10 10 10 VCC- GND 190 100 60 120 20 200 600 Typ Max Min 2.0 220 200 170 1.5 300 300 500 350 300 270 2.5 450 60 70 5 30 0.5 0.5 10 10 10 VCC- GND 190 100 60 120 20 200 600 25C Typ Max Min 2.0 220 200 170 1.5 300 300 500 350 300 270 2.5 450 60 70 5 30 0.5 0.5 10 10 10 VCC- GND 190 20 200 ps ps 600 85C Typ Max Unit GHz mV
fDATA tPLH, tPHL ts th tSKEW tJITTER
Gb/s ps
VINPP tr tf
Input Voltage Swing/Sensitivity (Differential Configuration) (Note 13) Output Rise/Fall Times @ 250 MHz (20% - 80%)
mV ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 12. Measured by forcing VINPPmin with 50% duty cycle clock source and VCC - 1400 mV offset. All loading with an external RL = 100 W. Input edge rates 150 ps (20%-80%). See Figure 13. 13. Input voltage swing is a single-ended measurement operating in differential mode. 14. RMS jitter with 50% Duty Cycle clock signal at 750 MHz. 15. Deterministic jitter with input NRZ data at PRBS 223-1 and K28.5. 16. Skew is measured between outputs under identical transition @ 250 MHz. 17. The worst case condition between Q0/Q0 and Q1/Q1 from either D0/D0 or D1/D1, when both outputs have the same transition.
400 OUTPUT VOLTAGE AMPLITUDE (mV) 350 300 250 200 150 100 50 0 85C 25C -40C
0
0.5
1
1.5
2
2.5
3
INPUT CLOCK FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fin) and Temperature (@ VCC = 3.3 V)
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NB6N14S
VOLTAGE (63.23 mV/div)
Device DDJ = 10 ps
TIME (58 ps/div)
Figure 5. Typical Output Waveform at 2.488 Gb/s with PRBS 223-1 and OC48 mask (VINPP = 100 mV; Input Signal DDJ = 14 ps)
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NB6N14S
VCC VCC VCC VCC
Zo = 50 W LVPECL Driver VT = VCC - 2.0 V
NB6N14S CLK 50 W 50 W LVDS Driver
Zo = 50 W VT = OPEN
NB6N14S CLK 50 W 50 W
Zo = 50 W
CLK
Zo = 50 W
CLK
VEE
VEE
VEE
VEE
Figure 6. LVPECL Interface
Figure 7. LVDS Interface
VCC
VCC
VCC
VCC
Zo = 50 W CML Driver VT = VCC
NB6N14S CLK 50 W 50 W HSTL Driver
Zo = 50 W VT =VEE
NB6N14S CLK 50 W 50 W
Zo = 50 W
CLK
Zo = 50 W
CLK
VEE
VEE
VEE
VEE
Figure 8. Standard 50 W Load CML Interface
Figure 9. Standard 50 W Load HSTL Interface
VCC
VCC
VCC
VCC
Zo = 50 W Differential Driver VT = VREF_AC
NB6N14S CLK 50 W 50 W Single-Ended Driver
Zo = 50 W VT = VREF_AC
NB6N14S CLK 50 W 50 W CLK
Zo = 50 W
CLK
VEE
VEE
VEE
VEE
Figure 10. Capacitor-Coupled Differential Interface (VT Connected to VREF_AC)
Figure 11. Capacitor-Coupled Single-Ended Interface (VT Connected to VREF_AC)
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NB6N14S
D D Q VOUTPP = VOH(Q) - VOL(Q) Q tPHL tPLH VINPP = VIH(D) - VIL(D)
Figure 12. AC Reference Measurement
LVDS Driver Device
Q
Zo = 50 W 100 W
D
LVDS Receiver Device
Q
Zo = 50 W
D
Figure 13. Typical LVDS Termination for Output Driver and Device Evaluation
QN VOS QN VOD
VOH
VOL
Figure 14. LVDS Output
VIH Vth VIL
IN
IN
Vth
IN
IN
Figure 15. Differential Input Driven Single-Ended
Figure 16. Differential Inputs Driven Differentially
VCC Vthmax VCC IN Vth Vthmin GND VIHmin IN VILmin GND VIHmax VILmax VCMR
VIH(MAX) VIL VIH VINPP = VIHD - VILD VIL VIH VIL(MIN)
Figure 17. Vth Diagram
Figure 18. VCMR Diagram
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NB6N14S
EN VCC/2 tS VINPP tpd VOUTPP tH VCC/2
/IN IN /Q Q
Figure 19. EN Timing Diagram
ORDERING INFORMATION
Device NB6N14SMNG NB6N14SMNR2G Package QFN-16, 3 X 3 mm (Pb-Free) QFN-16, 3 X 3 mm (Pb-Free) Shipping 123 Units / Rail 3000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NB6N14S
PACKAGE DIMENSIONS
16 PIN QFN CASE 485G-01 ISSUE C
D
A B
PIN 1 LOCATION
E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG DIM A A1 A3 b D D2 E E2 e K L MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.18 TYP 0.30 0.50
0.15 C 0.15 C 0.10 C
16 X
0.08 C
16X
L
NOTE 5 4
16X
K
1 16 16X 13
b BOTTOM VIEW 0.50 0.02
0.10 C A B 0.05 C
NOTE 3
AnyLevel and ECLinPS MAX are trademarks of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
CC CC
TOP VIEW (A3) SIDE VIEW D2
5
A A1
SEATING PLANE
C
SOLDERING FOOTPRINT*
0.575 0.022 3.25 0.128 0.30 0.012
e
8
EXPOSED PAD
EXPOSED PAD
9
E2
12
e
3.25 0.128
1.50 0.059
0.30 0.012
SCALE 10:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NB6N14S/D

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